Reset circuits have been routinely utilized as a supervisory device to monitor a power supply that supplies power to voltage sensitive electronic devices such as a microprocessor. The reset circuit performed a single function, that of asserting a reset signal whenever the power supply voltage dropped below a preset level. Once the reset signal had been asserted, the reset circuit continued to assert the reset signal until the power supply voltage had risen above a preset threshold for a predetermined period of time.
Such power supply voltage detection circuits could be falsely triggered when power was initially applied to the voltage sensitive electronic devices, and during power supply shutdown. By falsely triggering, the reset circuit could interrupt the operation of the voltage sensitive electronic devices.
FIG. 1 is an electrical block diagram of a prior art reset circuit 100 utilized to monitor the power supply supplying power to a voltage sensitive electronic device. The prior art reset circuit 100 generated a reset signal when the power supply voltage dropped below a predetermined value. The prior art reset circuit 100 included a bandgap reference 102, a resistor start-up circuit 104, a resistor divider comprising a resistor 106 and a resistor 108, and a comparator 110. The bandgap reference 102 provided two outputs, bgout supplying a voltage reference signal, Vbgout, and pbias providing a current reference signal, Vpbias. The resistor start-up circuit 104 provided two inputs, a Vcc input connected to and used to monitor the power supply voltage Vcc, and a bgout input connected to the bandgap reference 102, and one output res_div coupled to resistor 106. The comparator 110 provided three inputs, inm connected to the voltage reference signal, Vbgout, inp connected to the center tap of the voltage divider, and pbias connected to the current reference signal, Vpbia. The comparator 110 had a single output, vcc_ok, providing a reset signal when the power supply voltage dropped below a predetermined voltage during power down and power up.
In the prior art reset circuit 100, when the power supply voltage fell below the predetermined voltage, typically 2.1 volts, the bandgap circuit 102 could not be reliably used as a voltage reference and resulted in erroneous reset signals being generated. The resistor start-up circuit 104 was used to supply power to the resistor divider when the power supply voltage was greater than 2.1 volts, and disconnected power to the resistor divider when the power supply voltages fell below 2.1 volts. It will be appreciated that the actual predetermined voltage varied in value due to variations in processing of the reset circuit.
In normal operation, the comparator 110 provided an output, vcc_ok, which was a logic high when the power supply voltage, Vcc>Vrst, typically 2.63 volts. The current reference provided a constant current of approximately 250 nA and was used to stabilize the operation of the comparator 110. The predetermined power supply voltage was determined by comparing the voltage reference signal, Vbgout, with the output of the resistor divider. The bandgap reference 102 generated a voltage output of 1.25 volts. Resistor 106 and resistor 108 were selected to provide an output of 1.25 volts when the power supply voltage was at the predetermined power supply voltage.
FIG. 2 is an electrical diagram of the resistor start-up circuit 104 utilized in the prior art reset circuit of FIG. 1. The resistor start-up circuit 104 comprised transistor 206, transistor 208 and transistor 210 in branch 202. The source of transistor 206 was connected to Vcc; and the gate was connected to the voltage reference signal, Vbgout, generated by the bandgap reference 102. The drain of transistor 206 was connected to the gate and drain of diode connected transistor 208. The source of transistor 208 was connected to the gate and drain of diode connected transistor 210 and to the gate of transistor 216. The source of transistor 210 was connected to Vss (ground). Transistor 206 was a PMOS transistor, and transistor 208 and transistor 210 were NMOS transistors.
The resistor start-up circuit 104 also comprised transistor 212, transistor 214 and transistor 216 in branch 204. The source of transistor 212 was connected to Vcc, the gate was connected to the drain of diode connected transistor 212 and also to the gate of transistor 218. The drain of transistor 212 was connected to the gate and drain of diode connected transistor 214. The source of transistor 214 was connected to the drain of transistor 216. The source of transistor 216 was connected to Vss (ground). The source of transistor 218 was connected to Vcc while the drain was connected to resistor 106. The gate of transistor 218 was connected to the gate of transistor 212. Transistor 212 and transistor 218 were PMOS transistors, and transistor 214 and transistor 216 were NMOS transistors.
Transistor 206 functioned as a switched current source generating current when branch 202 was conducting. Branch 202 was conducting when                Vcc−Vbgout>Vtp206,        where Vtp206 is the threshold voltage of transistor 206, and        Vcc>Vsd206+Vtn208+Vtn210         where Vsd206 is the source to drain voltage across transistor 206, Vtn208 is the threshold voltage of transistor 208, and Vtn210 is the threshold voltage of transistor 210.        
Transistor 212 conducted when branch 204 was conducting. Branch 204 was conducting when                Vcc>Vtn214+Vtp212+Vds216         where Vtn214 is the threshold voltage of transistor 214, Vtp212 is the threshold voltage of transistor 212, and Vds216 is the drain to source voltage across transistor 216.        
In summary, when the voltage reference signal, Vbgout, which was coupled to the gate of transistor 206 rose sufficiently in voltage, the transistors of branch 202 were conducting. The current through transistor 210 was mirrored by transistor 216 in branch 204 and was set at twice the current of branch 202. When transistor 216 began conducting, transistor 212 and transistor 214 in branch 204 were also able to conduct. The current in branch 204 was set by establishing the w/l ratio of transistors 210 and 216 in a manner well known in the art. The current through transistor 212 when branch 204 was conducting was mirrored in transistor 218, generating the output signal, res_div, at the drain of transistor 218. When transistor 218 was conducting, Vcc was effectively supplied to the resistor divider because the current mirrored in transistor 218 was set 62.5 times the current through transistor 212, however, the resistance of the resistor divider is approximately 5.5 MegOhms, and thus the actual current delivered is typically less than 1 micro-Amp.
FIG. 3 is a graph depicting the operation of the prior art reset circuit of FIG. 1. Variations in the power supply voltage, Vcc, during power-up and power-down, depicted by waveform 302, is indicated by triangle symbols. The resistor divider voltage signal, depicted in waveform 304, is indicated by plus symbols. The voltage reference output, Vbgout, generated by the bandgap reference 102, depicted by waveform 306, is indicated by circle symbols. The reset output pulse, Vcc_ok, depicted by waveform 308, is indicated by asterisk symbols.
As can be by waveform 308, in addition to the desired reset pulse being generated by the reset circuit 100 during power-up, a transient pulse 310 was generated when the power supply voltage initially supplied to the reset circuit 100 reached a value between approximately 1.4 volts and 1.6 volts. The reset circuit 100 during power-down also generated a transient pulse 312 when the power supply voltage dropped below approximately 1.6 volts.
It is desirable to provide a means to improve the sensitivity of the power supply detection circuit by suppressing false triggering when powering up the power supply, and during power supply shutdown. It is also desirable to provide a means to reduce the current consumption of the power supply detection circuit.